Previous FPT
www.icfpt.org
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Advance Program
Here, ICFPT 2013 Program [pdf] is uploaded.
Schedule
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Dec 8
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Dec 9
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Dec 10
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Dec 11
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Dec 12
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Dec 13
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AM
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PM
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Wednesday, December 11, 2013
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Keynote Lecture III
Session Chair: Yajun Ha (National University of Singapore) |
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8:40-9:40 |
Why Put FPGAs in Your CPU Socket?
Prof. Paul Chow/Univ. of Toronto
[presentation pdf]
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Poster Session III |
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9:40-10:40 |
(Poster Presentation) |
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High-order Reconfigurable FIR Filter Design Based on Statistical Analysis of CSD Coefficients
Rui Jia, Fei Wang, Rui Chen, Xin-Gang Wang, Delong Shang and Hai-Gang Yang |
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Color configuration method for an optically reconfigurable gate array
Takumi Fujimori and Minoru Watanabe |
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Revisiting the reduction circuit: a case study for simultaneous architecture and precision optimisation
David Boland and George A. Constantinides |
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EasyPR - an Easy Usable Open Source PR System
Dirk Koch, Christian Beckhoff, Alexander Wold and Jim Torresen |
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A Hardware Implementation of Bag of Words and Simhash for Image Recognition
Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan and Lingli Wang |
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An FPGA-cluster-accelerated Match Engine for Content-based Image Retrieval
Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang and Lingli Wang |
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Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform Architecture Design
Hung-Lin Chao, Chun-Yang Peng, Cheng-Chien Wu, Ken-Shin Huang, Chun-Hsien Lu, Jih-Sheng Shen and Pao-Ann Hsiung |
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A high-speed FFT based on a six-step algorithm: Applied to a radio telescope for a solar radio burst
Hiroki Nakahara, Kazumasa Iwai and Hiroyuki Nakanishi |
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A Defect-tolerant Cluster in a Mesh SRAM-based FPGA
Arwa Ben Dhia, Rehman Saif Ur, Adrien Blanchardon, Lirida Naviner, Mounir Benabdenbi, Roselyne Chotin-Avot, Emna Amouri, Habib Mehrez and Zied Marrakchi |
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Reconfigurable Filtered Acceleration of Short Read Alignment
James Arram, Wayne Luk and Peiyong Jiang |
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Efficient methods for out-of-order load/store execution for high-performance soft processors
Henry Wong, Vaughn Betz and Jonathan Rose |
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Semantics-directed Machine Architecture in ReWire
Adam Procter, William Harrison, Ian Graves, Michela Becchi and Gerard Allwein |
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ZCluster: A Zynq-based Hadoop Cluster
Zhongduo Lin and Paul Chow |
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A Non-intrusive Portable Fault Injection Framework to Assess Reliability of FPGA-based Designs
Elyas Abolhassani Ghazaani, Zana Ghaderi and Seyed Ghassem Miremadi |
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3.1 High Performance Computing
Session Chair: Dirk Koch (University of Manchester) |
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10:40-11:00 |
Acceleration of Real-time Proximity Query for Dynamic Active Constraints
Thomas C.P. Chau, Ka-Wai Kwok, Gary C.T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y.K. Cheung and Wayne Luk |
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11:00-11:20 |
Dynamic Stencil: Effective Exploitation of Run-time Resources in Reconfigurable Clusters
Xinyu Niu , Jose G. F. Coutinho , Yu Wang and Wayne Luk |
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11:20-11:40 |
FlexGrip: A Soft GPGPU for FPGAs
Kevin Andryc, Murtaza Merchant and Russell Tessier |
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3.2 Physical Level EDA
Session Chair: Vaughn Betz (University of Toronto) |
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13:30-13:50 |
Maximizing Speed and Density of Tiled FPGA Overlays via Partitioning
Charles Eric LaForest and J. Gregory Steffan |
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13:50-14:10 |
Improving Clock-Rate of Hard-Macro Designs
Christopher Lavin, Brent Nelson and Brad Hutchings |
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14:10-14:30 |
Exploiting Stochastic Delay Variability on FPGAs with Adaptive Partial Rerouting
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George Constantinides and Peter Y. K. Cheung |
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14:30-14:50 |
Automated Multi-Device Placement, I/O Voltage Supply Assignment, and Pin Assignment in Circuit Board Design
Daniel Seemuth and Katherine Morrow |
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14:50-15:10 |
Break |
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3.3 High Level Synthesis II
Session Chair: Christian Plessl (University of Paderborn) |
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15:10-15:30 |
From Software Threads to Parallel Hardware in High-Level Synthesis for FPGAs
Jongsok Choi, Stephen Brown and Jason Anderson |
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15:30-15:50 |
StML: Bridging the Gap between FPGA Design and HDL Circuit Description
Dustin Peterson, Oliver Bringmann, Thomas Schweizer and Wolfgang Rosenstiel |
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15:50-16:10 |
Derivation of Efficient FSM from Loop Nests
Tomofumi Yuki, Antoine Morvan and Steven Derrien |
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16:10-16:30 |
An Automated Flow for the High Level Synthesis of Coarse Grained Parallel Applications
Vito Giovanni Castellana and Fabrizio Ferrandi |
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Design Competition (Final) |
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16:40-18:40 |
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