Previous FPT
www.icfpt.org
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Advance Program
Here, ICFPT 2013 Program [pdf] is uploaded.
Schedule
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Dec 8
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Dec 9
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Dec 10
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Dec 11
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Dec 12
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Dec 13
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AM
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PM
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Monday, December 9, 2013
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Keynote Lecture I
Session Chair: Hideharu Amano (Keio University) |
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9:00-10:00 |
Recent Advances in Die Stacking and 3D FPGA
Dr. Arif Rahman/Altera Corp.
[presentation pdf]
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Poster Session I |
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10:00-11:00 |
(Poster Presentation) |
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A High-Throughput FPGA Architecture for Parallel Connected Components Analysis Based on Label Reuse
Michael Klaiber, Donald Bailey, Silvia Ahmed, Yousef Baroud and Sven Simon |
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Teaching FPGA Security
Lilian Bossuet |
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Fast Boolean Matching Based on NPN Classification
Zheng Huang, Lingli Wang, Yakov Nasikovskiy and Alan Mishchenko |
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Multi-Personality Partitioning for Heterogeneous Systems
Anthony Gregerson, Aman Chadha and Katherine Morrow |
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A Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm using FPGA
Henry Block and Tsutomu Maruyama |
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Application-Specific Customisation of Market Data Feed Arbitration
Stewart Denholm, Hiroaki Inoue, Takashi Takenaka and Wayne Luk |
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A Connection-based Router for FPGAs
Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt |
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Flexible Hierarchy Ray Tracing on FPGAs
Sam Collinson and Oliver Sinnen |
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Design and Optimization of Heterogeneous Tree-based FPGA using 3D Technology
Vinod Pangracious, Zied Marrakchi and Habib Mehrez |
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NFA Reduction for Regular Expressions Matching Using FPGA
Vlastimil Košař, Martin Žádník and Jan Kořenek |
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Runtime Hardware/Software Task Transition Scheduling for Runtime-Adaptable Embedded Systems
Nathan Sandoval, Casey Mackin, Sean Whitsitt, Roman Lysecky and Jonathan Sprinkle |
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A Speculative Gather System for Cool Mega-Array
Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima and Hideharu Amano |
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1.1 Best Paper Candidate Session
Session Chair: Yoshiki Yamaguchi (University of Tsukuba) |
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11:00-11:20 |
Accelerating Validation of Time-Triggered Automotive Systems on FPGAs
Shreejith Shanker, Suhaib Fahmy and Martin Lukasiewycz |
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11:20-11:40 |
Exploiting Partially Defective LUTs: Why You Don't Need Perfect Fabrication
André DeHon and Nikil Mehta |
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11:40-12:00 |
Maximum Flow Algorithms for Maximum Observability During FPGA Debug
Eddie Hung, Al-Shahna Jamal and Steven J.E. Wilton |
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12:00-12:20 |
The Architecture and Placement Algorithm for A Uni-Directional Routing Based 3D FPGA
Junsong Hou, Heng Yu, Yajun Ha and Xin Liu |
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Solarflare Luncheon Session (Sponsored Session)
Session Chair: Kentaro Sano (Tohoku University) |
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12:20-14:00 |
Please have lunch with Solarflare's Co-Founder and CTO Steve Pope, on Monday, December 9th from 12:20 to 14:00PM.
Presentation slide [pdf]
Link to Solarflare's University Program
Enjoy a nice lunch and learn about Solarflare's University Program - a program that provides FPGA-based products for classroom instruction in computer science and computer engineering and enables computer science researchers to pioneer advances in Customized Compute through the use of Solarflare's AOE (ApplicationOnload Engine) hardware and development kits. |
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1.2 Architecture
Session Chair: Guy Lemieux (University of British Columbia) |
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14:00-14:20 |
COFFE: Fully-Automated Transistor Sizing for FPGAs
Charles Chiasson and Vaughn Betz |
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14:20-14:40 |
A Case for Hardened Multiplexers in FPGAs
S. Alexander Chin and Jason H. Anderson |
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14:40-15:00 |
Debugging Processors with Advanced Features by Reprogramming LUTs on FPGA
Satoshi Jo, Amir Masoud Gharehbaghi, Takeshi Matsumoto and Masahiro Fujita |
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15:00-15:20 |
Break |
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1.3 FPGA Appliactions I
Session Chair: Andre DeHon (University of Pennsylvania) |
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15:20-15:40 |
Virtual-to-Physical Address Translation for an FPGA-based Interconnect with Host and GPU Remote DMA Capabilities.
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto and Piero Vicini |
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15:40-16:00 |
Accelerating Iterative Algorithms with Asynchronous Accumulative Updates on FPGAs
Deepak Unnikrishnan, Sandesh Virupaksha, Lekshmi Krishnan, Lixin Gao and Russell Tessier |
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16:00-16:20 |
High Throughput, Tree Automata based XML Processing using FPGAs
Reetinder Sidhu |
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16:20-16:40 |
Transparent FPGA based Device for SQL DDoS Mitigation
Karthikeyan Pandiyarajan, Srijith Haridas and Kuruvilla Varghese |
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16:40-17:00 |
Break |
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1.4 Power-Aware and Dynamically Reconfigurable Systems
Session Chair: Jason Anderson (University of Toronto) |
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17:00-17:20 |
Discrete Event System Specification, Synthesis, and Optimization of Low-Power FPGA-based Embedded Systems
Tim Pifer, David Schwartz, Roman Lysecky, Chungman Seo and Bernard Zeigler |
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17:20-17:40 |
Optimizing Time and Space Multiplexed Computation in a Dynamically Reconfigurable Processor
Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshio Kitaoka, Katsumi Togawa, Koichiro Furuta and Toru Awashima |
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Welcome Reception |
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18:00-20:00 |
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Demo / Ph.D Forum / Design Competition Posters |
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18:00-20:00 |
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Demo
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An Open-Source SATA Core for Virtex-4 FPGAs
Cory Gorman, Paul Siqueira, and Russell Tessier |
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Direct Virtual Memory Access from FPGA for High-Productivity Heterogeneous Computing
Ho-Cheung Ng, Yuk-Ming Choi and Hayden Kwok-Hay So |
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Testing Reliability Techniques for SoCs with Fault Tolerant CGRA by using live FPGA Fault Injection
Johannes Maximilian Kühn, Thomas Schweizer, Dustin Peterson, Tommy Kuhn and Wolfgang Rosenstiel |
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Task level pipelining with PEACH2: an FPGA switching fabric for high performance computing
Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano and Taisuke Boku |
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Enhancing Communication On Automotive Networks Using Data Layer Extensions
Shreejith Shanker and Suhaib A. Fahmy |
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A Prototyping System for Hardware Distributed Objects with Diversity of Programming Languages
Takeshi Ohkawa, Takashi Yokota and Kanemitsu Ootsu
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Ph.D Forum
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Fast Simulation of Digital Spiking Silicon Neuron Model Employing Reconfigurable Dataflow Computing
Will Li, Shridhar Chaudhary, Ray Cheung, Takeshi Matsumoto and Masahiro Fujita |
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Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array
Peng Chen, Chao Wang, Xi Li and Xuehai Zhou
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Design Competition
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Implementation of a Highly Scalable Blokus Duo Solver on FPGA
Chester Liu
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From C to Blokus Duo with LegUp High-Level Synthesis
Jiu Cheng Cai, Mengyao Wang, Ruolong Lian, Andrew Canis, Jongsok Choi, Blair Fort, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Brown and Jason Anderson
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The Liquid Metal Blokus Duo Design
Erik Altman, Joshua Auerbach, David Bacon, Ioana Baldini, Perry Cheng, Stephen Fink, Rodric Rabbah and Sunil Shukla
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FPGA Blokus Duo Solver using a massively parallel architecture
Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji and Minoru Watanabe
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Artificial Intelligence of Blokus Duo on FPGA Using Cyber Work Bench
Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Yuki Katuta, Takushi Mitsuichi and Hideharu Amano
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An FPGA-based specific processor for Blokus Duo
Javier Olivito, Javier Resano and Carlos González
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An Implementation of Blokus Duo player on FPGA
Akira Kojima
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