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 Previous FPT
 www.icfpt.org
 
 
 | Advance Program 
     Here, ICFPT 2013 Program [pdf] is uploaded. 
 
 
 
Schedule
   
     
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	   Dec 8 | 
	   Dec 9 | 
	   Dec 10 | 
	   Dec 11 | 
	   Dec 12 | 
	   Dec 13 |  
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 Tuesday, December 10, 2013
 
 
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 | Keynote Lecture II Session Chair: Kazutoshi Kobayashi(Kyoto Institute of Technology)
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 | 8:40-9:40 | Reconfigurable chip Advantage compared with GPGPU from the compiler perspective Dr. Kazutoshi Wakabayashi/NEC Corp.
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 | Poster Session II |  
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 | 9:40-10:40 | (Poster Presentation) |  
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 | An Acceleration Method of Short Read mapping using FPGA Yoko Sogabe and Tsutomu Maruyama
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 | Quantum FPGA Architecture Design Jialin Chen, Lingli Wang and Bin Wang
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 | Real-time High-quality Stereo Vision System in FPGA Wen-Qiang Wang, Jing Yan, Ning-Yi Xu, Yu Wang and Feng-Hsiung Hsu
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 | High-Level Synthesis of Dynamic Data Structures: A Case Study Using Vivado HLS Felix Winterstein, Samuel Bayliss and George Constantinides
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 | Datapath Fault Tolerance for Parallel Accelerators James J. Davis and Peter Y. K. Cheung
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 | Hardware Acceleration of Biomedical Models with OpenCMISS and CellML Ting Yu, Chris Bradley and Oliver Sinnen
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 | sAES A High Throughput and Low Latency Secure Cloud Storage with Pipelined DMA Based PCIe Interface Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shuqin Ren and Khin Mi Mi Aung
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 | A 66.1 Gbps Single-pipeline AES on FPGA Qiang Liu, Zhenyu Xu and Ye Yuan
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 | Partially Reconfigurable Flux Calculation Scheme in Advection Term Computation Mohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
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 | FPGA-accelerated Key Search for Cold-Boot Attacks against AES Heinrich Riebler, Tobias Kenter, Christoph Sorge and Christian Plessl
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 | A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique Hongliang Su, Weihan Wang, Kuniaki Kitamori and Hideharu Amano
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 | Adaptive Compression for Instruction Code of Coarse Grained Reconfigurable Architectures Moo-Kyoung Chung, Jun-Kyoung Kim, Yeon-Gon Cho and Soojung Ryu
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 | 2.1 High Level Synthesis I Session Chair: Qiang Liu (Tianjin University)
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 | 10:40-11:00 | SOAP: Structural Optimization of Arithmetic Expressions for High-Level Synthesis Xitong Gao, Samuel Bayliss and George Constantinides
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 | 11:00-11:20 | Making Domain-Specific Hardware Synthesis Tools Cost-Efficient Nithin George, David Novo, Tiark Rompf, Martin Odersky and Paolo Ienne
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 | 11:20-11:40 | System-Level FPGA Device Driver with High-Level Synthesis Support Vipin Kizhepatt, Shreejith Shanker, Dulitha Gunasekara, Suhaib Fahmy and Nachiket Kapre
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 | 11:40-12:00 | Bitwidth-Optimized Hardware Accelerators with Software Fallback Ana Klimovic and Jason Anderson
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 | 2.2 FPGA Applications II Session Chair: Tsutomu Maruyama (University of Tsukuba)
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 | 13:30-13:50 | Implementation of High Performance Hardware Architecture of OpenSURF Algorithm on FPGA Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang and Lingli Wang
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 | 13:50-14:10 | TROJANUS: An Ultra-Lightweight Side-Channel Leakage Generator for FPGAs Sebastian Kutzner, Axel Poschmann and Marc Stöttinger
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 | 14:10-14:30 | Real-time and Low Power Embedded L1-Optimization Solver Design Zhi Ping Ang and Akash Kumar
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 | 14:30-14:50 | A Low Latency Kernel Recursive Least Squares Processor using FPGA Technology Yeyong Pang, Shaojun Wang, Yu Peng, Nick Fraser and Philip H.W. Leong
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 | 14:50-15:10 | Break |  
 
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 | 2.3 (Special Session) Coarse Grain Reconfigurable Architectures for Graphics Session Chairs: Soojung Ryu (SAMSUNG Electronics) and Steve Wilton (University of British Columbia)
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 | 15:10-15:30 | Efficient Execution of Augmented Reality Applications on Mobile Programmable Accelerators Jason Jong Kyu Park, Yongjun Park and Scott Mahlke
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 | 15:30-15:50 | An OpenCL Optimizing Compiler for Reconfigurable Processors Jeongho Nah, Jun Lee, Hongjune Kim, Jinseok Lee, Seok Joong Hwang, Donghoon Yoo and Jaejin Lee
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 | 15:50-16:10 | Real-time Ray Tracing on Coarse-grained Reconfigurable Processor Jaedon Lee, Youngsam Shin, Won-Jong Lee, Soojung Ryu and Jeongwook Kim
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 | 16:10-16:30 | Mobile GPU Shader Processor based on Non-blocking Coarse Grained Reconfigurable Arrays Architecture Kwontaek Kwon, Sungjin Son, Jeongsoo Park, Jeongae Park, Sangoak Woo, Seokyoon Jung and Soojung Ryu
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