Why Put FPGAs in Your CPU Socket?
Paul Chow (University of Toronto, Canada)
Abstract: Ever since FPGAs were invented, there has been great
interest in using them as computing devices, and with the logic
densities of today's devices, many interesting functions have been
shown to have significant performance and energy benefits when
implemented in FPGAs. However, when an application requires the
combination of a high-performance CPU and an FPGA accelerator, the
effectiveness of the FPGA is highly determined by the latency and
bandwidth between the CPU, the CPU memory system and the FPGA and its
memory system. Putting FPGAs into the CPU socket is one way to
address this issue. This talk will present the history, the
advantages and disadvantages, the challenges, architectures,
programming models and applications of "in-socket" accelerator
Paul Chow is a Professor in the Department of Electrical and
Computer Engineering at the University of Toronto where he holds the
Dusan and Anne Miklas Chair in Engineering Design. Prior to joining
UofT in 1988 he was at the Computer Systems Laboratory at Stanford
University, Stanford, CA, as a Research Associate, where he was a
major contributor to an early RISC microprocessor design called
MIPS-X, one of the first microprocessors with an on-chip instruction
cache and the root of many concepts used in processors today. His
research interests include high performance computer architectures,
reconfigurable computing, embedded and application-specific
processors, and field-programmable gate array architectures and
applications. Paul was the Program Chair for the 2008 ACM/SIGDA
International Symposium on Field-Programmable Gate Arrays (FPGA 2008),
the premier conference for FPGAs and General Chair for FPGA 2009. In
2011, he was the Program Chair for the IEEE Symposium on
Field-Programmable Custom Computing Machines (FCCM 2011), the main
conference for the reconfigurable computing area. He was the FCCM
2012 General Chair. In addition, Paul is on the technical program
committee for the four main FPGA conferences: FPGA, FCCM, FPL, FPT.
On the entreprenurial front, Paul was a co-founder of AcceLight
Networks, which built a high-capacity, carrier-grade, optical
switching system in 2000 using FPGAs. He is also a co-founder of
ArchES Computing Systems, which is developing embedded and
reconfigurable computing technology. URL:
Recent Advances in Die Stacking and 3D FPGA
Arifur Rahman (Altera, USA)
Abstract: Die stacking technology with high-bandwidth interconnect
is enabling new product architectures and capabilities. Although 3D
integration, where TSVs are incorporated in active device layers, is
the Holy-Grail of die stacking, the early phase of technology adoption
is driven by passive silicon interposer (2.5D) based integration
scheme or some variants of it. This presentation will provide an
overview of recent advances in die stacking and FPGA application
trends which are driving the need for stacking technologies. I will
present some of the industry challenges in technology integration and
design infrastructure and how they are being addressed to enable
broader technology adoption.
Arifur Rahman is an Architect at Altera, where he led
Product Architecture team and currently leads FPGA based System in
Package product development. He has more than 15 years of research
and product development experience in circuits and architecture,
design methodology, manufacturing technology, and supply chain
strategy. His expertise includes all aspects of advanced die
stacking, from technology development to design methodology and
product architecture. He incubated and productized silicon interposer
based FPGAs at Xilinx and co-invented stacked silicon interconnect
(SSI) products. Prior to Altera, he worked at Xilinx, Agere Systems,
Lattice Semiconductor, and Polytechnic University, NY. Arif holds a
PhD degree from MIT in Electrical Engineering and an MBA from Santa
Clara University. He has authored numerous articles and has been
granted 56 patents. He serves in the program committee of IEEE Custom
Integrated Circuits Conference (CICC) and was the Co-Chair of the 9th
International RTI 3-D Architectures for Semiconductor Integration and
Packaging conference in 2012. He is a senior member of IEEE.
Reconfigurable chip Advantage compared with GPGPU from the compiler perspective
Kazutoshi Wakabayashi (NEC Corporation)
Abstract: This presentation discusses how FPGA or coarse grained reconfigurable processor is superior to CPU/GPGPU from the view point of C compiler. Initially, we introduce the architectural characteristic of CPU, GPGPU and fine grained and coarse grained reconfigurable process with FSM+Datapath model. Then, we explain what kind of applications can be accelerated with "FPGA and C-based High Level Synthesis Tool" better than GPGPU according to the compiler techniques (freedom of compiler parallelization).
Kazutoshi Wakabayashi received his B.E. and M.E. degrees and Ph.D from the University of Tokyo in 1984, 1986 and 2006. He was a visiting researcher at Stanford University during 1993 and 1994. He joined NEC Corporation in Kawasaki Japan in 1986 and he is currently a Senior Principal Researcher of Central Research Labs. NEC Corporation.
Dr.Wakabayashi has been engaged in the research and development of VLSI, CAD systems; high-level and logic synthesis, formal and semi-formal verification, system-level simulation, HDL, emulation, HLS and floorplan links, and reconfigurable computing.
He served on executive committee or organizing committee of some international conference including: ASP-DAC'09 General Chair, CODES+ISSS'09 Co-Technical Program Chair. a Secretary of Steering Committee of ASPDAC, and Executive Committee for ICCAD and DAC, Tutorial Chair of ASPDAC2006, Steering Committee of ITC-CSCC (09-).
He has served on the program committees for several international conferences including: DAC, ICCAD, DATE, ASP-DAC, ISSS, SASIMI, and ITC-CSCC, ISCAS, VLSI-TSI, SBCCI, VLSI Design, ESS, ISLP and so on.
Also, he has served as a general chair, a secretary, and a Technical Program Committee member for a number of Japanese conferences, including: Institute of Electronics, Information and Communication Engineers of Japan (IEICE), the Information Processing Society of Japan (IPSJ), System LSI WS, Karuizawa WS.
He is currently chair of SIG on VLSI design methodology of IEICE, and elected member of IEICE. He was an associate editor of Transactions on IEICE on VLSI CAD, DAEM. He is a rep. of CEDA (Council for EDA) of IEEE. He is also a member of IEEE, IPSJ, and IEICE.
He received the IPSJ Kiyasu Special Industrial Achievement Award 2011, the Yamazaki-Teiichi Prize in 2004, and the IPSJ Convention Award in 1988, Sakai Kinen Special Award in 2001, and the NEC Distinguished Contribution Award in 1993 for his logic synthesis system and in 1999 for his formal verification, and in 2006 for his High Level Synthesis. His C-based Synthesis and Verification tool suite called "CyberWorkBench" received a Grand prize of "LSI of the Year 2003" and "LSI of the Year 2007".