Mr. Ken Chapman

Xilinx Inc. Senior Staff Engineer, Applications Specialist
United Kingdom

" Highly Efficient Designs: Art, Magic or Engineering? "

I have an efficient design. Good, but what does that mean? Is it efficient because it was implemented using efficient design tools or was it the result of using the square root of Boltzsmanns constant as the seed for the placement algorithm? Surely it cannot have anything to do with Engineers; what could they possibly know about efficient design?

Biography

Ken left school at the age of 16 to become a precision instrument maker. Whilst turning brass by day, his evenings were spent studying  Electronic Engineering at Southend Technical College where over the  next 4 years he obtained TEC and HNC qualifications. Along the way Ken  moved to a small electronics company working through assembly,  inspection, and test departments. At the ripe old age of 20 he  returned to full time education and obtained a BSc in Electronic and  Electrical Engineering from the University of Surrey.

University was followed by 4 years working for a large defence  company. The design and system integration of naval RADAR surveillance  and counter measures systems emphasized that there was far more  involved to bringing large systems to work reliably in the field for many years.

In 1989, Ken implemented a set of designs using Xilinx XC3090 devices.  At that time FPGA technology was still in its infancy, 20MHz was a  challenge and design implementation was a very manual task but Ken  loved it! A couple of years later, he was invited to join Xilinx where  he has been an Applications Engineer for 21 years.

Ken is best known for the 8-bit PicoBlaze family of processors which  reflect his passion for optimum FPGA design techniques. He holds  several patents relating to his pioneering implementation of DSP  algorithms in FPGA devices and has written and taught courses around  the world on this subject. In more recent years, key areas of work  have been optimum design to reduce the cost of high volume products,  design for reliability and SEU mitigation techniques.

Outside of work, Ken is a private pilot and takes to the skies when  the British weather allows.

 

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Dr. David Broman

UC Berkeley/Linkoping University
CA, USA

" Execution time should be as short as possible, but not shorter "

In general-purpose computing, execution time is a quality factor where the faster is better, not more correct. In cyber-physical systems (CPS)--which mix computations, networks, and physical processes--timing is, however, a correctness criterion. The problem is not to make execution time as short as possible, but to make it short enough to meet real-time deadlines. As a consequence, as long as deadlines are met, the objective is to optimize other parameters, such as frequency/voltage, area, and memory. This talk will discuss an ongoing project at UC Berkeley, called the precision timed (PRET) infrastructure, where execution time is a correctness criterion. The infrastructure consists of an intermediate language, a compiler, and a specialized microprocessor--extended with instructions and semantics for handling time.

Biography

David Broman is currently a visiting scholar at UC Berkeley, USA, working in the Ptolemy group at the Electrical Engineering and Computer Science department. He is an assistant professor at Linköping University in Sweden, where he also received his Ph.D. in computer science in 2010. David's research interests include programming and modeling language theory, compiler technology, software engineering, and mathematical modeling and simulation of cyber-physical systems. He has worked five years within the software security industry, co-founded the EOOLT workshop series, and is member of the Modelica Association and the Modelica language design group.