Research Topics
研究テーマ
Networking Architecture Based on Data-Driven Processors
A data-driven (non-von Neumann) processor is the realization of a data-driven execution model in which operations become executable after all of their operands arrive.
The data-driven processor realizes multiprocessing without overheads such as the context-switching found in sequential (von Neumann) processors. It can therefore guarantee real-time processing even when multiplicity (e.g., the number of IP packets processed simultaneously) increases, as long as the processing load stays under the design target.
This real-time multiprocessing feature is indispensable for networking, where real-time constraints are strictly demanded even as traffic increases — that is, the data-driven processor is inherently suitable for networking processing. Based on this processor, we study networking architecture straddling multiple research fields: networking schemes, processor architecture, and circuit implementation.
Patents granted (Japan) Patents pending (domestic & international)
Recent Research Results
Highlights from our recent publications
FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline and Its Refinement
The two-phase bundled-data circular self-timed pipeline (TBCSTP) is an appealing asynchronous circuit: its relatively fast, on-demand data transfer leads to high power-performance efficiency, and its circular datapath can realize not only iterative or recursive operations but also program execution. We have pioneered a circuit design method that enables TBCSTP implementation on commercial FPGAs. This paper presents a refinement that enhances the potential throughput by introducing shortcuts for the main transfer control signals, and clarifies the intrinsic timing constraints for static timing analysis of TBCSTP circuits.
Self-timed pipelineAsynchronous circuitsFPGA
Shuji Sannomiya, Senri Yoshikawa, Makoto Iwata, "FPGA-oriented Two-phase Bundled-data Circular Self-timed Pipeline and Its Refinement," Journal of Information Processing, Vol.34, pp.535-547, Jun. 2026. DOI: 10.2197/ipsjjip.34.535
Implementation of Self-timed Data-driven Processor for IoT Computing Platform
This paper presents an implementation of the self-timed data-driven processor (STDDP), which embodies the data-driven processing scheme — a non-von Neumann architecture — and realizes zero-runtime-overhead real-time multiprocessing on a self-timed (global-clock-less) pipeline circuit. Referring to RV32I, the base integer instruction set of RISC-V, as a benchmark for instruction complexity and variety, we introduced a register-like internal memory into the STDDP, stipulated an RV32I-comparable instruction set, and prototyped two processors realizing it.
Data-driven processorRISC-VIoT
Jun Nakayama, Shuji Sannomiya, Makoto Iwata, "Implementation of Self-timed Data-driven Processor for IoT Computing Platform," in Proc. of International Electrical Engineering Congress (iEECON2026), 2026.
Stream-Thru Processing Scheme for IoT Computing Platform
We proposed the Stream-Thru processing scheme (STPS), a processor architectural scheme that achieves the guaranteed throughput essential for making IoT devices robust against dynamic load fluctuation. The data-driven processing scheme passively initiates operations whenever their operands arrive; in practice, the number of data flowing in a processor may therefore exceed a given capacity, making the expected throughput unachievable. STPS addresses this architectural issue.
Guaranteed throughputReal-time multiprocessingIoT
Shuji Sannomiya, Senri Yoshikawa, Makoto Iwata, Hiroaki Nishikawa, "Stream-Thru Processing Scheme for IoT Computing Platform," Proc. of 2025 IEEE Region 10 Symposium (TENSYMP), Jul. 2025.
Anomaly Detection in IoT Computing Platform Using Self-Timed Data-Driven Processor
We proposed an external, lightweight monitoring circuit for detecting anomalies such as cyberattacks and failures in computing platforms. External monitoring is preferable because of its natural immunity to anomalies in the target platform and its minimal consumption of the platform's processing power; however, existing methods require a processor-scale additional circuit. By exploiting the characteristics of the STDDP, we realized lightweight external monitoring suitable for resource-limited IoT devices. This paper won the Best Paper Award at IEEE CCWC 2025.
Anomaly detectionSecurityIoT
Hajime Maeda, Shuji Sannomiya, Keisuke Kameyama, Hotaka Takizawa, Makoto Iwata, Hiroaki Nishikawa, "Anomaly Detection in IoT Computing Platform Using Self-Timed Data-Driven Processor," Proc. of IEEE 15th Annual Computing and Communication Workshop and Conference (CCWC), pp. 00901-00908, Jan. 2025.
EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline
Self-timed pipelines (STPs) are attractive for their power-performance efficiency, and a circular STP is necessary to directly implement iterative or recursive operations and circular datapaths for program execution. We pointed out that conventional four-phase bundled-data circuits can lead to design failures or unacceptably deteriorated throughput because industry-standard EDA tools improperly interpret their configuration — especially in functions such as pipeline branching and data copy/erasure — and proposed a circular STP design method including a low-latency handshake circuit for commercial FPGAs.
Self-timed pipelineEDAFPGA
Senri Yoshikawa, Shuji Sannomiya, Makoto Iwata, Akira Sato, Hiroaki Nishikawa, "EDA-oriented FPGA Circuit Design Method for Four-phase Bundled-data Circular Self-timed Pipeline," Journal of Information Processing, Vol.31, pp.495-508, Aug. 2023. DOI: 10.2197/ipsjjip.31.495
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