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Workshop Program

Workshop Site
Kenshu-shitsu 1/2, 3rd Floor
Tiruru (Okinawa Gender Equality Center),
3-11-1 Nishi Naha-shi Okinawa, 900-0036, Japan
(MAP)

 

 
Wednesday, May 30
 
Workshop Registration
13:00-18:00 HEART2012 Registration
 
FPGA Design Contest 2012
-- Connect 6 Revenge --
Session chair: Hideharu Amano
13:15-13:25 Opening
13:25-14:50 Preliminary Round
14:50-15:00 Break
15:00-16:40 Final Round
16:45-16:50 Closing
 
COFFEE/TEA BREAK
16:50-17:15Coffee/Tea Break
 
Industrial Keynote Speech
Session chair: Tsutomu Maruyama
17:15-18:15 DAPDNA: A Coarse-Grained Dynamically Reconfigurable Architecture
-- Introduction of Application Examples and New Products --

Akifumi Watanabe
Tokyo Keiki Inc.
 
HEART 2012 Welcome Reception
19:00-20:30HEART 2012 Welcome Reception
FPGA Design Contest 2012 Poster Session & Awards Ceremony
(The workshop site closes at 21:00.)

 

 
Thursday, May 31
 
Workshop Registration
09:00-18:00 Registration
 
Opening
Session chair: Wayne Luk
09:30-09:40 Opening
 
Keynote Talk: Invited Lecture 1
Session chair:
09:40-10:40 Cyper-physical MPSoC Systems
-- Adaptive Multi-Core Architectures for Future Mobility & Technologies --

Prof. Dr.-Ing. Jürgen Becker
Karlsruhe Institute of Technology, Germany
 
Session 1: Best Paper Candidates
Session chair: Yukinori Sato
10:40-11:10 FPGA-based Connect6 Solver with Hardware-Accelerated Move Refinement
Kentaro Sano and Yoshiaki Kono
11:10-11:40 Roberts: Reconfigurable Platform for Benchmarking Real-time Systems
Thomas C.P. Chau, Wayne Luk and Peter Y. K. Cheung
11:40-12:10 An Augmented Reality System with Coarse-Grained Device
Kei Kinoshita, Daisuke Takano, Tomoyuki Okamura, Tetsuhiko Yao and Yoshiki Yamaguchi
 
COFFEE/TEA BREAK
12:10-12:30Coffee/Tea Break
 
Luncheon Seminar Session
Moderator: Tsuyoshi Hamada
12:30-13:50
 
COFFEE/TEA BREAK
13:50-14:10Coffee/Tea Break
 
Session 2: System Software
Session chair: Kenneth Kent
14:10-14:40 Session Types: Towards Safe and Fast Reconfigurable Design
Nicholas Ng, Nobuko Yoshida, Xinyu Niu, Kuen Hung Tsoi and Wayne Luk
14:40-15:10 A Low Overhead Abstract Architecture for FPGA Resource Management
Rizwan Syed, Yajun Ha and Bharadwaj Veeravalli
15:10-15:40 Modelling Reconfigurable Systems in Event Driven Simulation
Kuen Hung Tsoi, Tobias Becker and Wayne Luk
 
COFFEE/TEA BREAK
15:40-15:50Coffee/Tea Break
 
Session 3: Poster Short Presentations
Session chair: David Thomas
15:50-15:55 Improving System Reliability using Dynamic Functional Verification on CGRAs
Johannes Maximilian Kühn, Sven Eisenhardt, Thomas Schweizer, Tommy Kuhn
and Wolfgang Rosenstiel
15:55-16:00 A Domain Specific Language and Toolchain for Runtime Binary Acceleration
Takaaki Miyajima, David Thomas and Hideharu Amano
16:00-16:05 A Novel Compiler to Maximize Throughput of Data Reordering Unit
on Wireless Baseband Processor
Nozomi Ishihara, Tomoyoshi Kobori, Katutoshi Seki and Masao Ikekawa
16:05-16:10 An Automatic Code Optimization for High Level Synthesis
Mao Hatto, Takaaki Miyajima and Hideharu Amano
16:10-16:15 An Implementation and Evaluation of MapReduce Framework with
Thread Virtualization Environment for Cell Broadband Engine Clusters
Masahiro Yamada, Tetsuya Nakahama, Masato Yoshimi, Hideharu Amano and Shinpei Nomura
16:15-16:20 Link Aggregate Traffic Prediction Based on Multiple Data-Driven Traffic Predictions for Pseudo-Adaptive Routing in Network-on-Chip
Vee Yeow Edwin Benedict Khoo and Yajun Ha
16:20-16:25 ASIP Instruction Selection with the Encoding-Space Constraint
for High Performance
Chiu Yun Hung, Hsin I Lin and Yi Wen Wang
16:25-16:30 FPGA based Stereo Vision System for Future Video Tolling
Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk and Huazhong Yang
16:30-16:35 Enhancing MPI Delivery Protocol in NoC-Based MPSoC System
Eduard Fernandez-Alonso, David Castells and Jordi Carrabina
16:35-16:40 Trace Generation in Many-Soft-Cores
David Castells, Eduard Fernandez-Alonso and Jordi Carrabina
 
Poster Presentations & COFFEE/TEA BREAK
16:40-17:40HEART Poster session & FPGA Contest Poster Papers
FPGA Contest Poster Papers:

Connect6 Game-Tree Reduction based on Image Processing and Its Positional Symmetric Property
Toru Yabuki, Suguru Ochiai, Yoshiki Yamaguchi and Yuetsu Kodama

FPGA Connect6 Solver with Hardware Sort Units
Retsu Moriwaki, Takashi Yoza, Yuki Kamikubo, Yuki Torigai, Takahiro Watanabe, Yuji Aoyama, Masato Seo and Minoru Watanabe

High-Level Synthesis of an Open Source Connect-6 Player
Sumanta Chaudhuri, Justin Wong and Takaaki Miyajima

A Simple Connect6 Threat-Based Hardware Design
Sen Wang, Andrew Somerville and Kenneth B. Kent

 
HEART 2012 Banquet
18:30-21:00HEART 2012 Banquet
Kane ohe room, Pacific Hotel Okinawa

 

 
Friday, June 1
 
Workshop Registration
09:00-17:30 Registration
 
Session 4: Applications
Session chair: Hayden Kwok-Hay So
10:00-10:30 FPGA Acceleration of CDO Pricing based on Correlation Expansions
Zheng Zhi Shun and Tsutomu Maruyama
10:30-11:00 On a Wideband Fast Fourier Transform for a Radio Telescope
Hiroki Nakahara, Hiroyuki Nakanishi and Tsutomu Sasao
11:00-11:30 High Performance Phylogenetic Analysis on CUDA-compatible GPUs
Cheng Ling, Khaled Benkrid and Tsuyoshi Hamada
 
Lunch Break
11:30-13:00Lunch Break
 
Keynote Talk: Invited Lecture 2
Session chair: Kentaro Sano
13:00-14:00 DEGIMA: The greenest accelerator-based supercomputer in the TOP500 list
Prof. Tsuyoshi Hamada
Nagasaki University, Japan
 
Session 5: Platforms and frameworks for accelerators
Session chair: Khaled Benkrid
14:00-14:30 Energy-Efficient Dataflow Computations on FPGAs using Application-Specific Coarse-Grain Architecture Synthesis
Colin Yu Lin and Hayden Kwok-Hay So
14:30-15:00 Effort, Resources, and Abstraction Vs Performance in High-Level Synthesis: Finding New Answers to an Old Question
Jamshaid Sarwar Malik, Paolo Palazzari and Ahmed Hemani
15:00-15:30 Performance Comparison of GPU Programming Frameworks with the Striped Smith-Waterman Algorithm
Takeshi Kakimoto, Keisuke Dohi, Yuichiro Shibata and Kiyoshi Oguri
 
COFFEE/TEA BREAK
15:30-15:50Coffee/Tea Break
 
Session 6: Innovative Accelerator Devices
Session chair: Kazuya Tanigawa
15:50-16:20 PASTIS: Photonic Arbitration with Scalable Token Injection Scheme
Julien Tribino, Antoine Trouvé, Hadrien Clarke and Kazuaki Murakami
16:20-16:50 0.18 um CMOS Process High-sensitive Optically Reconfigurable Gate Array VLSI
Takahiro Watanabe and Minoru Watanabe
16:50-17:20 A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes
Shogo Nakaya, Makoto Miyamura, Noboru Sakimura, Yuichi Nakamura and Tadahiko Sugibayashi
 
Closing Remarks
Session chair: Yukinori Sato & Khaled Benkrid
17:20-17:30Closing
 
 
Copyright 2010-2012, HEART Organizing Committee   
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