Invited Keynote Lecture 1 [09:10-10:10, May 31]

Prof. Dr.-Ing. Juergen Becker

Cyper-physical MPSoC Systems
- Adaptive Multi-Core Architectures for future Mobility & Technologies-

Prof. Dr.-Ing. Jürgen Becker,
Chief Higher Education Officer
Karlsruhe Institute of Technology -KIT,


Jürgen Becker is Full Professor for Embedded Electronic Systems in the department of Electrical Engineering and Information Technology at the Karlsruhe Institute of Technology – KIT. His actual research is focused on industrial-driven System-on-Chip (SoC) integration with emphasis on adaptivity, e.g. dynamically reconfigurable hardware architecture development and application especially in automotive, image/video processing, security and communication systems. Prof. Becker is Head of the Institute for Information Processing (ITIV) and Department Director of Electronic Systems and Microsystems (ESM) at the Computer Science Research Center (FZI). From 2001- 2005 he has been Co-Director of the International Department at the former Universitaet Karlsruhe (TH). He is author and co-author of more than 300 peer-reviewed scientific papers, and active as general and technical pro-gram chairman of national / international conferences and workshops. He is executive board member of the german IEEE section, Board member of the GI/ITG Technical Committee of Architectures for VLSI Circuits, Associate Editor of the IEEE Transactions on Computers, and Senior Member of the IEEE. Since October 2005 Prof. Becker is Vice-Rector ("Prorektor") for Studies and Teaching at Universitaet Karlsruhe (TH), which currently emerged into the new Karlsruhe Institute of Technology – KIT – the consequent and unique merger of a large national research lab in the Helmholtz Society as well as of a prominent state university of Baden-Wuerttemberg in Germany.

Lecture Summary

The field of embedded electronic systems, nowadays also called cyper-physical systems, is still emerging. A cyber-physical system (CPS) is a system featuring a tight combination of, and coordination between, the system's computational and physical elements. Today, a pre-cursor generation of cyber-physical systems can be found in areas as diverse as aerospace, automotive, chemical processes, civil infrastructure, energy, healthcare, manufacturing, transportation, entertainment, and consumer appliances. This generation is often referred to as embedded systems. In embedded systems the emphasis tends to be more on the computational elements, and less on an intense link between the computational and physical elements. Multipurpose adaptivity and reliability features are playing more and more of a central role, especially while scaling silicon technologies down according to Moore°≠s benchmarks. Leading processor and mainframe companies are gaining more awareness of reconfigurable computing technologies due to increasing energy and cost constraints. My view is of an °»all-win-symbiosis°… of future silicon-based processor technologies and reconfigurable circuits/architectures. Dynamic and partial reconfiguration has progressed from academic labs to industry research and development groups, providing high adaptivity for a range of applications and situations. Reliability, failure-redundancy and run-time adaptivity using real-time hardware reconfiguration are important aspects for current and future embedded systems, e.g. for smart mobility in automotive, avionics, railway, etc.. Thus, scalability, as we have experienced for the last 35 years is at its end as we enter new phases of technology and certification within safety-critical application domains. Beyond the capabilities of traditional reconfigurable fabrics (like FPGAs), the so-called Multi-/Many-Core solutions are confirmed on the future semiconductor roadmaps. This requires new solutions for programming and integrating such kind of parallel and heterogenous architectures and platforms, e.g. especially in safety-critical application domains like automotive, avionics and railway.

I addition: Nano Era with corresponding circuits/architectures allow for micro-mechanical switches that enable new memory and reconfiguration technologies with the advantage of online chip adaptivity and non-volatility. Transient faults may lead to unreliable information processing as information in nano-sized devices is much less. Power consumption and related problems present a challenge where information is processed within a smaller area/volume budget. This includes the consideration of appropriate fault tolerance techniques and especially the discussion of necessary efficient and online self-repairing mechanisms for driving such kind of future silicon and non-silicon based technologies and architectures.

This keynote will finally discuss in detail the corresponding challenges and specifically outline the promising perspectives for future multi-/many-core as well as dynamically reconfigurable, complex, adaptive and reliable systems-on-chip, for embedded and also general purpose computing systems.

Invited Keynote Lecture 2 [13:00-14:00, June 1]

Tsuyoshi Hamada

The greenest accelerator-based supercomputer in the TOP500 list

Dr. Tsuyoshi Hamada,
2009 Gordon Bell Prize
Nagasaki Advanced Computing Center, Nagasaki University,

[[Lecture Slide]] / [[Movie (.mov)]]


Tsuyoshi Hamada is the head of the massively parallel computing division and the deputy director of the Nagasaki Advanced Computing Center (NACC), and an associate professor at Nagasaki University. Tsuyoshi Hamada obtained his PhD in 2006 from the University of Tokyo. From 2006 to 2008, he was a Special Postdoctoral Researcher at RIKEN. In 2008, he became an assistant Professor at Nagasaki University, and was promoted to Associate Professor in 2010. He has worked on massively parallel architectures based on FPGAs and GPUs. In 2004, he wrote a compiler PGR for FPGAs to automate the programming of reconfigurable systems. In 2005, he designed a FPGA-based computer PROGRAPE-4 and achieved 243 GFlops/board and 7.7 TFlops for the entire system. Since 2006, he has been focusing on GPUs. In 2007, he released a CUDA library for N-body problems, CUNBODY. His cluster in Nagasaki started out in 2008 with 32 8800GT GPUs. In April 2008, he extended this to 128 8800GTS cards, and in November 2008 to 256 8800GTS cards. In April 2009, he acquired another 256 9800GTX cards, and in August 2009 another 288 of the GTX295 cards. With his large GPU cluster (DEGIMA), he achieved a sustained performance of 158 TFlops and $7.2/GFlops, which led to the Gordon Bell prize for price/performance at SC2009. In 2010, he changed the interconnect to Infiniband and achieved 190 TFlops. His paper has been selected as a Gordon Bell Honorable Mention for SC2010. The latest DEGIMA is ranked 6th on the Green500 List of Nov. 2011.

Lecture Summary

At the frontline of high performance computing, we have seen great success on producing faster, cheaper, and smaller systems. One good example of such progress is the GPU-based DEGIMA cluster, which characterises itself for being one of the most cost-efficient and power-efficient supercomputers in the world. However, the same advances that have driven HPC have intensified power related challenges. In this talk we will discuss energy management techniques used in DEGIMA that allow us to maximise performance for a given power budget or improve power-efficiency for a given performance target.

Industrial Keynote


DAPDNA: A Coarse-Grained Dynamically Reconfigurable Architecture
-- the introduction of application examples and its new products --


[[Lecture Slide]]


TOKYO KEIKI was established in Koishikawa, Tokyo in 1896 as Japan's first measuring instrument manufacturer of pressure gauges and other measuring devices. In 1930, the head office moved to Kamata, Tokyo. The company°«s current areas of business extend to the aerospace, marine, railways, and industrial machinery markets. In 2009, the company°«s printing inspection systems business unit released a product which incorporated DAPDNA-2 DRPs to analyze camera images. In 2010, Tokyo Keiki assumed the business and development of DAPDNA from IPFlex Inc.


DAPDNA was born from the venture business of IPFlex Inc. in JAPAN, 2002, with a prototype chip, called DAPDNA-HP. In 2004, DAPDNA-2 was released as the world's first general purpose commercial DRP. DAPDNA-IMX was released in 2007 for image processing applications. Please refer to this web page.

Lecture Summary

We provide a brief introduction of DAPDNA architecture with examples of applications and information on a newly developed chip. This presentation is intended to underscore the continuous advances in this DRP architecture and technology by Tokyo Keiki.

Speaker's Biography

Akifumi Watanabe is a software engineer who has been involved with this technology since he joined IPFlex. He is in charge of designing the DAPDNA-FW II development software that develops application systems for DAPDNA devices.

  • 2001: Joined IPFlex Inc.
  • 2008-2009: Visiting engineer of Yamanaka Lab at Keio University in study of DAPDNA applications in networking.
  • 2009: Joined Tokyo Keiki Inc.
  • 2010-present: Continue development of DAPDNA-FW II


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