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HEART2012 ended. Thank you so much!
See you in Heart2013, Edinburgh, UK.

HEART2012 Post Proceedings have been published by ACM CAN!
Keynote Lecture Slides by Prof. Tsuyoshi Hamada was uploaded!
Industrial Keynote Lecture Slides by Mr. Akifumi Watanabe was uploaded!
Luncheon Panel Discussion Slide by Prof. Khaled Benkrid was uploaded.

HEART2012 Paper Awards:

Best Paper Award:
  • FPGA-based Connect6 Solver with Hardware-Accelerated Move Refinement
    Kentaro Sano and Yoshiaki Kono
Best Poster Paper Award:
  • FPGA based Stereo Vision System for Future Video Tolling
    Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk and Huazhong Yang

Overview

The HEART workshop is an international forum for state-of-the-art researches on high-performance computing with reconfigurable architectures and/or specialized accelerators. The third meeting of HEART will be held in Okinawa, Japan.

Scope

The scope of the meeting includes, but is not limited to:
  • Architectures and systems:
    • Novel systems/platforms for efficient acceleration based on FPGA, GPU, CELL/B.E and other devices
    • Heterogeneous processors/systems for scalable, high-performance, high-reliability and/or low-power computation
    • Reconfigurable/configurable hardware and systems including IP-cores, embedded systems, SoCs and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
    • High-performance custom-computing processors/systems
    • Novel architectures and device technologies that can be applied to efficient acceleration, including many-core architectures, NoC architectures, 3D-stacking technologies and optical devices
  • Software and applications:
    • Novel applications for efficient acceleration systems/platforms, and custom computing
    • Compiler techniques and programming languages for efficient acceleration systems/platforms, including many-core processors, GPUs, FPGAs and other reconfigurable/custom processors
    • Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
    • Performance evaluation and analysis for efficient acceleration
    • High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems

FPGA Design Contest 2012 (Connect6 Revenge)

connect6

Important dates (GMT, UTC+0):

Scenes and the streets of Okinawa

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