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Call for papers [PDF]
Important dates (GMT, UTC+0):
Summary:
The 3rd International Workshop on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
new research on accelerators and the use of reconfigurable
technologies for high-performance and/or power-efficient
computation. Submissions are solicited on a wide variety of topics
related to the acceleration for high-performance computation,
including but not limited to:
- Architectures and systems:
- Novel systems/platforms for efficient acceleration based on FPGA, GPU, CELL/B.E and other devices
- Heterogeneous processors/systems for scalable, high-performance, high-reliability and/or low-power computation
- Reconfigurable/configurable hardware and systems including IP-cores, embedded systems, SoCs and cluster/grid/cloud computing systems for scalable, high-performance and/or low-power processing
- High-performance custom-computing processors/systems
- Novel architectures and device technologies that can be applied to efficient acceleration, including many-core architectures, NoC architectures, 3D-stacking technologies and optical devices
- Software and applications:
- Novel applications for efficient acceleration systems/platforms, and custom computing
- Compiler techniques and programming languages for efficient acceleration systems/platforms, including many-core processors, GPUs, FPGAs and other reconfigurable/custom processors
- Run-time techniques for acceleration, including Just-in-Time compilation and dynamic partial-reconfiguration
- Performance evaluation and analysis for efficient acceleration
- High-level synthesis and design methodologies for heterogeneous, reconfigurable and/or custom processors/systems
In order to encourage open discussion on future directions, the
program committee will provide higher priority for papers that present
highly innovative and challenging ideas.
We will accept regular and short papers for oral and poster
presentation, respectively. All the accepted regular papers will be
published in the post-proceedings that will be published as a
special issue of ACM SIGARCH Computer Architecture News (CAN) and
will also be available in ACM Digital Library. By submitting your work
to the HEART2012 workshop, you grant permission for ACM to publish the
material in print and digital formats in ACM's Computer Architecture
News and the ACM archive. The short papers will be included in the
workshop handout distributed at the workshop. One of the authors must
attend the workshop and present their work as a condition of
publication.
All papers must be no more than 6 pages (two columns, US letter size,
10 points for main body text) in length and prepared in PDF
format. For double-blind review, manuscripts must NOT identify
authors; names of authors, affiliations, e-mail addresses and
self-references should be blanked out. Papers that identify authors
may be rejected without review. Full formatting and submission
instructions are available at the HEART2012 web-site.
Keynote Lectures
In addition to the presentation of accepted papers, we will also have two keynote lectures by:
- Dr. Tsuyoshi Hamada
- Deputy Director of the Nagasaki
- Advanced Computing Center, Nagasaki University, Japan
- Prof. Jurgen Becker
- Chief Higher Education Officer
- Karlsruhe Institute of Technology, Germany
and one industrial talk by
FPGA Design Contest
Moreover, we will hold the FPGA design-contest "Connect6 Revenge"
on 30 May, 2012, in conjunction with the technical committee on
reconfigurable Systems (RECONF) of IEICE, Japan. The awards ceremony
of the contest will be held at the welcome reception on 30 May.
Contest participants are required to register by following instructions
at this page.
Workshop Committees:
Workshop co-chairs:
Program co-chairs:
Finance chair:
Publication co-chairs:
Publicity co-chairs:
Local arrangements chair:
Design Contest co-chairs:
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Program committee
- Ali Akoglu, University of Arizona, USA
- Philip Brisk, University of California, Riverside, USA
- Florent de Dinechin, Ecole Normale Supérieure de Lyon, FR
- Yajun Ha, National University of Singapore, SG
- Martin Herbordt, Boston University, USA
- Yohei Hori, National Institute of Advanced Industrial Science and Technology, JP
- Paolo Ienne, EPFL, CH
- Tomonori Izumi, Ritsumeikan University, JP
- Nachiket Kapre, Imperial College London, UK
- Dirk Koch, University of Oslo, NO
- Herman Lam, University of Florida, USA
- Philip Leong, University of Sydney, AU
- Tsutomu Maruyama, University of Tsukuba, JP
- Smail Niar, University of Valenciennes and Hainaut-Cambresis, FR
- Miquel Pericás, Tokyo Institute of Technology, JP
- Gregory Peterson, University of Tenessee, USA
- Hayden Kwok-Hay So, University of Hong Kong, HK
- Yiannis Sourdis, Chalmers University of Technology, SE
- Henry Styles, Xilinx, USA
- Bharat Sukhwani, IBM T. J. Watson Research Center, USA
- Thomas D. VanCourt, Akamai Technologies, USA
- Wim Vanderbauwhede, Glasgow University, UK
- Minoru Watanabe, Shizuoka University, JP
- Stephan Wong, Delft University of Technology, NL
- Masato Yoshimi, Doshisha University, JP
- Chiwai Yu, City University of Hong Kong, Hong Kong, HK
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