University of Tsukuba | Grad. Scho. Syst. and Info. Eng. | Dept. Comp. Sci. | List of Courses
Moritoshi Yasunaga, Kenji Kanazawa
E-Mail {yasunaga}_at_cs_dot_tsukuba_dot_ac_dot_jp, {kanazawa}_at_cs_dot_tsukuba_dot_ac_dot_jp
Office hours SB1106 Fri.:13:00-15:00
Cource# 01CH405
Area Information Engineering
Basic/Advanced 基礎科目
Course style Lecture
Term SprAB
Period Tue5,6
Room# 3B301
Keywords Integrated Circuits,Transistor,CMOS,Logic Circuits,Memory Circuits,FPGA (Field Programmable Gate Array),CAD,Hardware Description Language,Software and Hardware co-design,Printed Circuit Board,VLSI applications
Prerequisites Knowledge on logic circuits in freshman and sophomore years are required, but it on VLSI engineering in junior and senior years are not required necessarily.
relation degree program competence Knowledge Utilization Skills,International Skills,Research Skills,Expert Knowledge
Outline It lectures on VLSI around the fundamental concept: circuit model, implementation, design methodology, applications et al. The problems of VLSI technology in the near future are discussed from the viewpoint of the circuit scale and the high integration.
Course plan 1st week:Integrated Circuits and Logic Gates
  • Hardware Implementation of Logic Gates Using Switches
  • Direct Implementation of Boolean Algebra
  • 2nd week:Semiconductor and Transistors
  • pn-junction and MOS transistor
  • 3rd week:Transistors and Logic Circuits
  • Logic circuits based on MOS transistors
  • Operation Speed and Power Consumption
  • 4th week:Memory VLSIs
  • DRAMと and RAM
  • Flash Memory
  • 5th VLSI Process and Configurations:
  • Semiconductor Process
  • Full/Semi-custom VLSIs and FPGA
  • 6th week:VLSI Design methodology―Logic synthesis (1)―
  • logic algebra, logic functions, functional completeness, 2-level circuit optimization
  • 7th week:VLSI Design methodology―Logic synthesis(2)―
  • multi-level circuits, multi-level circuit optimization, technology mapping
  • 8th week:VLSI Design methodology―Place and Route―
  • global placement, detailed placement, routing methodologies
  • 9th week:VLSI Design methodology―High-Level synthesis―
  • control and data flow graph, scheduling, resource binding
  • 10th week:VLSI Design methodology―Validation & Testing―
  • equivalence checking, timing validation, fault models and test algorithms
  • Textbook Handouts and "Integrated Circuit Engineering"(集積回路工学) [in Japanese] (by Moritoshi Yasunaga, Morikita Publisher)
    • John P. Uyemura,
      "Intrroduction to VLSI Circuits and Systems", Wiley Text Books
    • Neil H.E. Weste and Kamran Eshraghian,
      "Principles of CMOS VLSI Design", Addison Wesley
    • Yuan Taur and Tak H. Ning,
      "Fundamentals of Modern VLSI Devices", Cambridge University Press
    • Carver Mead and Lynn Conway,
      "Introduction to VLSI Systems", Addison-Wesley
    Evaluation Grading is on assignment-report basis. Assignment reports are evaluated based not only on their correctness but on their clarity and originality:
    A+ (100-95: Excellent)
    A  (94-80: Good)
    B  (79-70: Satisfactory)
    C  (69-60: Minimal Pass)
    D  (59- : Poor)
    TF / TA