Off-loading LET generation to PEACH2:
A switching hub for high performance GPU clusters

Power Performance Profiling of 3-D Stencil Computation
on an FPGA Accelerator for Efficient Pipeline Optimization

Understanding Outstanding Memory Request Handling Resources in GPGPUs

A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface

Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq

ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface
for Reconfigurable Accelerators

A Transfer-Aware Runtime System
for Heterogeneous Asynchronous Parallel Execution

Efficient Mapping and Allocation of Execution Units to Task Graphs
using an Evolutionary Framework

Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA

Breadth First Search on Cost-efficient Multi-GPU Systems

Interface Based Memory Synthesis of Image Processing Chains in FPGA

High Throughput Sketch Based Online Heavy Hitter Detection on FPGA

A Configurable Architecture for Sparse LU Decomposition on Matrices
with Arbitrary Patterns

Stream Computation of Shallow Water Equation Solver
for FPGA-based 1D Tsunami Simulation

Parallel Genetic Algorithms on Multiple FPGAs