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Workshop Program
| Tuesday, June 1 |
| Opening & Invited Talk 1 Session chair: Wayne Luk |
| 08:55-09:00 | Opening |
| 09:00-09:40 | Reconfigurable Computing in the Multi-Core Era Khaled Benkrid |
| Session 1: FPGA-based Applications Session chair: Kentaro Sano |
| 09:50-10:15 | A Temporal Coding Hardware Implementation for Spiking Neural Networks Marco Nuno-Maganda, Cesar Torres-Huitzil
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| 10:15-10:40 | Implementation and Evaluation of an Arithmetic Pipeline on FLOPS-2D:Multi-FPGA System Hirokazu Morisita, Kenta Inakagata, Yasunori Osana, Naoaki Fujita, Hideharu Amano |
| 10:40-11:05 | Efficient Reconfigurable Design for Pricing Asian Options Anson H.T. Tse, David B. Thomas, K.H. Tsoi, Wayne Luk |
| 11:05-11:30 | An FPGA-based fast classifier with high generalization property
Tadayoshi Horita, Itsuo Takanami |
| Lunch Break |
| Session 2: Frameworks Session chair: Yoshiki Yamaguchi |
| 12:45-13:10 | Dynamic Vectorization in the E2 Dynamic Multicore Architecture Aaron Smith, Andrew Putnam, Doug Burger |
| 13:10-13:35 | Binary acceleration using coarse-grained reconfigurable architecture Jong Kyung Paek, Kiyoung Choi, Jongeun Lee |
| 13:35-14:00 | Implementation of a Programming Environment with a Multithread Model for Reconfigurable Systems Keisuke Dohi, Yuichiro Shibata, Tsuyoshi Hamada, Tomonari Masada, Kiyoshi Oguri, Duncan A. Buell |
| 14:00-14:25 | Runtime Multitasking Support on Reconfigurable Accelerators Mojtaba Sabeghi, Hamid Mushtaq, Koen Bertels |
| 14:25-14:50 | Programming Framework for Clusters with Heterogeneous Accelerators Kuen Hung Tsoi, Peter Pietzuch, Anson Tse, Wayne Luk |
| Session 3: Accelerators Session chair: Yuichiro Shibata |
| 15:00-15:25 | An efficient CELL library for Lattice Quantum Chromodynamics Claude Tadonki, Gilbert Grodidier, Olivier Pene |
| 15:25-15:50 | Software-based predication for AMD GPUs Ryan Taylor, Xiaoming Li |
| 15:50-16:15 | Multipliers for Floating-Point Double Precision and Beyond on FPGAs Sebastian Banescu, Florent de Dinechin, Bogdan Pasca, Radu Tudoran |
| 16:15-16:40 | Prototype Implementation of Array-Processor Extensible over Multiple FPGAs for Scalable Stencil Computation Kentaro Sano, Wang Luzhou, Satoru Yamamoto |
| 16:40-17:05 | Dynamic Power Reduction of FPGA-based Reconfigurable Computers using Precomputation Chi-Chiu Tsang, Hayden Kwok-Hay So |
| Invited Talk 2 Session chair: Hideharu Amano |
| 17:15-17:55 | Custom Computing for Efficient Acceleration of HPC Kernels Kentaro Sano |
| Closing Session chair: Yoshiki Yamaguchi |
| 17:55-18:00 | Closing |
| Poster Session & Exhibition Reception |
| 18:15-20:15 | Poster Session |
| Wednesday, June 2 |
| Extended Poster Session (in conjunction with ICS2010) |
| 15:30-16:30 | Poster Session |
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Poster Presentations
The Harris algorithm revisited on the CELL processor
Claude Tadonki, Lionel Lacassagne, Tarik Saidani, Joel Falcou, Khaled HamidouchePower-Delay and Energy-Delay Tradeoffs for Matrix-Matrix Multiplication on FPGAs
Colin Yu Lin, Zheng Zhang, Ngai Wong and Hayden Kwok-Hay SoImproving the Reliability of FPGA system by using TMR and Partial Reconfiguration
Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori SueyoshiPower-aware FPGA Routing Structure and Design Tools
Junya Eto, Shoichi Nishida, Motoki Amagasaki, Masahiro Iida and Toshinori SueyoshiAn FPGA Implementation of Line-Based Architecture 2-D Discrete Wavelet Transform Using Impulse C
Takaaki MIYAJIMA, Hideharu AMANO, Masatoshi ARAIExploring Hybrid-Core Computing for Option Pricing Applications
Brahim Betkaoui, David B. Thomas, Wayne LukFCHC lattice gas model on Playstation3
Yusuke Arai, Yoshiki Yamaguchi, Moritoshi YasunagaScalable FPGA System for High-Performance computing with Large-Scaled Hardware
Hironori Nakajo, Ryuichi Sakamoto, Takefumi Miyoshi, Satoshi Funada, Tsutomu YoshinagaA four-context optically reconfigurable gate array using a laser array attachment
Takayuki Mabuchi and Minoru Watanabe
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