並列処理アーキテクチャ特論

並列処理アーキテクチャ特論_E
Instructor(s)	Hiroshi Tomiyasu, Shuji Sannomiya
E-Mail	Hiroshi Tomiyasu: tomiyasu@cs.tsukuba.ac.jp Shuji Sannomiya: san@cs.tsukuba.ac.jp
URL
Office hours	RD303, Monday 15:15-16:30
Cource#	01CH402
Area	Computer Engineering
Basic/Advanced
Course style	Lecture
Term	秋AB
Period	月3,4
Room#	3B302
Keywords	data-driven processor, self-timed pipeline, low-power-cosnumption
Prerequisites	Undergraduate level understanding of fundamental computer architecture
relation degree program competence	Knowledge Utilization Skills,International Skills,Research Skills,Expert Knowledge
Goal
Outline	We discuss about parallel processing architecture taking topic of the basic issues and also the latest research cases, for example Data Flow Model, from the view point of the system specification / verification methods and realization. Then, we mention not only achievement of high function and high performance but also maintenance of information system, the point of continuity view and the coming parallel and distributed processing system.
Course plan	1st-2nd week What is parallel processing architecture? - Introduction of historical background and necessity of parallel processing architecture 3rd-4th week Realization of parallel processing architecture - Parallel processing architecture which has been realized until now and its characteristics 5th-8th week Research of parallel processing system and development case - Introduction of parallel and distributed architecture which is given attention 9th-10th week A view for the future of parallel processing architecture - What information system as infrastructure should be and evolution toward networking architecture of networking architecture of parallel processing architecture
Textbook	Course materials and handouts will be provided.
References
Evaluation	Your grade will be determined by evaluating reports' score. The criteria below will be used as a guide. 90-100 A+ 80-89 A 70-79 B 60-69 C
TF / TA
Misc.	Open in an even number year.