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Workshop Program
| Workshop Site |
Room 611, Gabor Seminar Room,
Electrical Engineering Building, Imperial College London
(Enrty 18 in this map)
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| Wednesday, June 1 |
| Workshop Pre-registration
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| 15:30-16:30 |
Pre-registration
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| Thursday, June 2 |
| Workshop Registration
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| 08:00-08:50 |
Registration
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| Opening
Session chair: Wayne Luk
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| 08:50-09:00 |
Opening
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| Session 1: Systems and Tools I
Session chair: Hayden So
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| 09:00-10:00 |
The Challenges of Writing Portable, Correct and High Performance Libraries for GPUs or How to Avoid the Heroics of GPU Programming
Professor Miriam Leeser
Northeastern University, USA
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| 10:00-10:30 |
Power Profiling and Optimization for Heterogeneous Multi-Core Systems
Kuen Hung Tsoi and Wayne Luk
Imperial College London, United Kingdom
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| COFFEE/TEA BREAK |
| 10:30-11:00 | Coffee/Tea Break |
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| Session 2. GPU Applications
Session chair: Kuen-Hung Tsoi
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| 11:00-11:30 |
GPU Accelerated CAE Using Open Solvers and the Cloud
Serban Georgescu and Peter Chow
Fujitsu Laboratories of Europe Limited, United Kingdom
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| 11:30-12:00 |
Design Space Exploration of Adaptive Beamforming Acceleration for Bedside and Portable Medical Ultrasound Imaging
Junying Chen*, Billy Y. S. Yiu*, Brandon K. Hamilton**, Alfred C. H. Yu*, and Hayden K.-H. So*
* The University of Hong Kong, Hong Kong
** The University of Cape Town, South Africa
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| 12:00-12:30 |
GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing
Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri and Takahumi Fujimoto
Nagasaki University, Japan
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| Lunch Break |
| 12:30-14:00 | Lunch Break |
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| Session 3. Architectures I
Session chair: Eric Senn
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| 14:00-14:30 | CoreSymphony: An Efficient Reconfigurable Multi-core Architecture Tomoyuki Nagatsuka, Yoshito Sakaguchi, Takayuki Matsumura, and Kenji Kise
Tokyo Institute of Technology, Japan |
| 14:30-15:00 | An FPGA-based Scalable Simulation Accelerator for Tile Architectures Shinya Takamaeda-Yamazaki, Ryosuke Sasakawa, Yoshito Sakaguchi, and Kenji Kise
Tokyo Institute of Technology, Japan |
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| Session 4: Poster Session Short Presentations
Session chair: Yoshiki Yamaguchi
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| 15:00-15:30 |
Automatic Fusions of CUDA-GPU Kernels for Parallel Map
Jan Fousek, Jiŕí Filipovič, and Matúš Madzin
Masaryk University, Czech Republic
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| A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU
Kohei Matsunobu, Keisuke Dohi, Yuichiro Shibata, and Kiyoshi Oguri
Nagasaki University, Japan
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| Multicore Reconfiguration Platform an alternative to RAMPSoC
Dominik Meyer and Bernd Klauer
Helmut Schmidt University, Germany
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| Parallelism Level Impact on Energy Consumption in Reconfigurable Devices
Robin BONAMY*, Daniel CHILLET*, Olivier SENTIEYS*, and Sebastien BILAVARN**
* CAIRN, University of Rennes, France
** University of Nice Sophia Antipolis, France
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| Power and Area Optimisation in Heterogeneous 3D Networks-on-Chip Architectures
Michael Opoku Agyeman and Ali Ahmadinia
Glasgow Caledonian University, United Kingdom
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| COFFEE/TEA BREAK AND POSTER PRESENTATIONS |
| 15:30-16:00 | COFFEE/TEA BREAK AND POSTER PRESENTATIONS |
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| Session 5. FPGA Applications I
Session chair: Yuichiro Shibata |
| 16:00-16:30 |
Domain-Specific Programmable Design of Scalable Streaming-Array for Power-Efficient Stencil Computation
Kentaro Sano*, Satoru Yamamoto*, and Yoshiaki Hatsuda**
* Tohoku University, Japan
** Kobo, Co. Ltd., Japan
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| 16:30-17:00 |
An Implementation of Out-Of-Order Execution System for Acceleration of Computational Fluid Dynamics on FPGAs
Takayuki Akamine*1, Kenta Inakagata*1, Yasunori Osana*2, Naoyuki Fujita*3, and Hideharu Amano*1
*1 Keio University, Japan
*2 Ryukyu University, Japan
*3 ARD Japan Aerospace Exploration Agency, Japan
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| 17:00-17:20 | Heterogeneous Embedded Architecture for Target Recognition in a Driver Assistant System
Haisheng Liu, Smail Niar, Yassin El-Hillali and Atika Rivenq
Université de valenciennes, France
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| HEART 2011 Banquet (supported by KEIO GCOE) |
| 19:00-22:00 | HEART 2011 Banquet |
| Friday, June 3 |
| Workshop Registration
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| 08:00-09:00 |
Registration
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| Session 6. Systems and Tools II
Session chair: Hideharu Amano
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| 09:00-10:00 |
Surviving the end of frequency scaling with reconfigurable dataflow computing
Dr. Oliver Pell
Vice-president, Maxeler Technologies, United Kingdom
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| 10:00-10:30 |
KPN2GPU: An Approach for Discovery and Exploitation of Fine-Grain Data Parallelism in Process Networks
Ana Balevic and Bart Kienhuis
University of Leiden, Netherlands
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| COFFEE/TEA BREAK |
| 10:30-11:00 | Coffee/Tea Break |
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| Session 7. FPGA Applications II
Session chair: Khaled Benkrid
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| 11:00-11:30 |
High Speed CRC with 64-bit generator polynomial on an FPGA
Amila Akagić and Hideharu Amano
Keio University, Japan
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| 11:30-11:50 |
A Biologically Plausible Real-time Spiking Neuron Simulation Environment Based on a Multiple-FPGA Platform
Shufan Yang and TM McGinnity
University of Ulster, United Kingdom
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| 11:50-12:10 |
Parallelization of the channel width search for FPGA routing
Hiroomi Sawada, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, and Toshinori Sueyoshi
Kumamoto University, Japan
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| Lunch Break |
| 12:10-13:40 | Lunch Break |
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| Session 8. Architecture II
Session chair: Kentaro Sano
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| 13:40-14:00 |
A study of FPGA-based flexible SIMD processor
Shoji Tanabe, Takuya Nagashima and Yoshiki Yamaguchi
University of Tsukuba, Japan
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| 14:00-14:20 |
Augmenting DR-ASIP Flexibility Through Multi-Mode Custom Instructions
Antoine Trouvé and Kazuaki Murakami
Kyushu University, Japan
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| 14:20-14:40 |
A MEMS writer system embedded for a programmable optically reconfigurable gate array
Shinya Kubota and Minoru Watanabe
Shizuoka University, Japan
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| 14:40-15:00 |
FPGA modeling for SoC design exploration
Dominique Blouin*1, Eric Senn*1, Robin Bonamy*2, Daniel Chillet*2, Sébastien Bilavarn*3, and Christian Samoyeau*4
*1 Universite de Bretagne-Sud, France
*2 Universite de Rennes, France
*3 Universite de Nice Sophia Antipolis, France
*4 InPixal, France
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| Closing Remarks
Session chair: Hideharu Amano
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| 15:00-15:15 | Closing |
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