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                            CALL FOR PAPERS

                  The First International Workshop on
     Highly Efficient Accelerators and Reconfigurable Technologies
                            -- HEART2010 --

                    in Tsukuba, Japan, June 1, 2010
   <http://www.cs.tsukuba.ac.jp/~yoshiki/HEART/HEART2010/index.html>

                        Held in conjunction with
        International Conference on Supercomputing (ICS-2010)
                    <http://www.ics-conference.org/>
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IMPORTANT DATES (JST, UTC+9):
  - Paper submission:       April 17, 2010 ( EXTENDED FIRM )
  - Author notification:    April 28, 2010 ( EXTENDED )
  - Camera-ready deadline:  May    3, 2010 ( EXTENDED )
  - Workshop date:          June   1, 2010

The 1st International Workshop on Highly Efficient Accelerators and
Reconfigurable Technologies (HEART) is a forum to present and discuss
new research on accelerators and the use of reconfigurable technologies
for high-performance and/or power-efficient computation. Submissions
are solicited on a wide variety of topics related to the acceleration
for high-performance computation, including but not limited to:

 * Architectures and systems:
   - Reconfigurable/configurable hardware and systems including
     IP-cores, embedded systems and/or SoCs for scalable,
     high-performance and/or low-power computation
   - High-performance custom-computing systems based on reconfigurable
     technologies including FPGAs
   - Grid/cluster computing with FPGAs, other reconfigurable
     technologies and accelerators such as GPGPUs and Cell/B.E.s 
   - Novel architectures and devices that can be applied to efficient
     acceleration, including many-core architectures, NoC architectures,
     optical devices/interconnection

 * Software and applications:
   - Novel applications for high-performance reconfigurable systems
     and accelerators including GPGPUs and Cell/B.E.
   - Compiler techniques and programming languages for reconfigurable
     acceleration systems and other accelerators such as GPGPUs and
     Cell/B.E.
   - Run-time systems and the use of run-time reconfigurability for
     acceleration
   - Performance evaluation and analysis of reconfigurable acceleration
     systems and other accelerators such as GPGPUs and Cell/B.E.

In order to encourage open discussion on future directions, the program
committee will provide higher priority for papers that present highly
innovative and challenging ideas.

The submission procedure will be announced on the HEART2010 WEB in detail.
Papers are limited to 6 pages (two columns in ACM conference format),
and must be prepared in PDF format. For double-blind review, manuscripts
must NOT identify authors; names of authors, affiliations, e-mail
addresses and self-references should be blanked out. Papers that
identify authors may be rejected without review.

All the accepted regular-papers are going to be included in the post
proceedings that will be published as a special issue of ACM SIGARCH
Computer Architecture News (CAN) in this year. The papers will also
be available in ACM Digital Library. By submitting your work to the
HEART2010 workshop, you grant permission for ACM to publish the
material in print and digital formats in ACM's Computer Architecture
News and the ACM archive.


For more information, please visit
 <http://www.cs.tsukuba.ac.jp/~yoshiki/HEART/HEART2010/index.html>.

For any questions, please contact the Secretariat
 <heart2010-inquiry@islab.cs.tsukuba.ac.jp>.


Workshop Committees
-------------------

Workshop Co-chairs:

 - Hideharu Amano (Keio University, JP)
 - Wayne Luk (Imperial College London, UK)

Program Co-chairs:

 - Kentaro Sano (Tohoku University, JP)
 - Yuichiro Shibata (Nagasaki University, JP)
 - Yoshiki Yamaguchi (University of Tsukuba, JP)

Publication Chair:

 - Hironori Nakajo (Tokyo University of Agriculture and Technology, JP)

Program Committee

 - Akira Nagoya (Okayama University, JP)
 - David Thomas (Imperial College London, UK)
 - Khaled Benkrid (University of Edinburgh, UK)
 - Kiyoshi Oguri (Nagasaki University, JP)
 - Masahiro Iida (Kumamoto University, JP)
 - Marco D. Santambrogio (Massachusetts Institute of Technology, US)
 - Masato Yoshimi (Doshisha University, JP)
 - Naoyuki Fujita (JAXA, JP)
 - Proshanta Saha (IBM T.J. Watson Research Center, US)
 - Ray C.C. Cheung (City University of Hong Kong, HK)
 - Shuichi Ichikawa (Toyohashi University of Technology, JP)
 - Tomonori Izumi (Ritsumeikan University, JP)
 - Tsutomu Maruyama (University of Tsukuba, JP)
 - Yajun Ha (National University of Singapore, SG)
 - Yasunori Osana (Seikei University, JP)
 - Yasushi Inoguchi (JAIST, JP)
 - Yohei Hori (Chuo University, JP)

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Co-sponsored by
   Reconfigurable Systems, Information and Systems Society, IEICE, JAPAN
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