"忘れてはならないのは、創造的な仕事は集中しなければ進まないことである。"
"我々が反省すべきは「早めにやっておけばよかった」ではなく、「もっと集中すべきだった」である。"
-- 松尾 豊(ネルー値論文)

論文誌

• Yusuke Yamagiwa, Yuki Kawahara, Kenji Kanazawa, and Moritoshi Yasunaga
  ``A Highly-Scalable Self-Organizing Map Accelerator on FPGA and its performance evaluation''
  International Journal of Artificial Life and Robotics, Springer, pp. 94--100, 2024
• Kenji Kanazawa
  ``FPGA Acceleration of Swap-Based Tabu Search for Solving Maximum Clique Problems''
  Journal of Information Processing Vol. 30, pp.513-524, 2022
  
• Kenji Kanazawa and Tsutomu Maruyama
  ``An Approach for Solving SAT/MaxSAT-encoded Formal Verification Problems on FPGA''
  IEICE Transactions on information and systems Vol.E100-D No.8, pp.1807-1818, 2017
  
• 監物 香保里，金澤 健治，森 大和，相部 範之，安永 守利
  ``FPGAを用いた画像処理応用のためのMonotone Chainアルゴリズムの高速計算''
  電子情報通信学会論文誌 Vol.J100-D No.1, pp.1-13, 2017
  
• Kenji Kanazawa and Tsutomu Maruyama
  ``An Approach for Solving Large SAT Problems on FPGA''
  ACM Transactions on Reconfigurable Technology and Systems Vol.4 No.1 Article 10, 21 pages, 2010
  
• 金沢 健治，丸山 勉
  ``FPGAを用いた大規模な充足可能性問題の高速計算''
  電子情報通信学会論文誌 Vol.J90-D No.10, pp.2713-2722, 2007
  
• 金沢 健治，丸山 勉
  ``FPGAを用いたWSATアルゴリズムの高速計算''
  電子情報通信学会論文誌 Vol.J89-D No.6, pp.1173-1181, 2006
  

査読付国際会議

• Ryosuke Yanagisawa and Kenji Kanazawa
  ``FPGA Implementation of Sparse Matrix Vector Multiplication with Small-Scale Matrix Element Router''
  IEEE 43rd International Conference on Consumer Electrornics (ICCE-2025), 5 pages, Las Vegas, United States, 2025
• Jiheng Wang, Kenji Kanazawa, and Moritoshi Yasunaga
  ``FPGA Implementation of Minimum Spanning Tree Calculation Towards Application for Capacitated Vehicle Routing Problems''
  IEEE 42nd International Conference on Consumer Electrornics (ICCE-2024), 3 pages, Las Vegas, United States, 2024
• Yusuke Yamagiwa, Kenji Kanazawa, and Moritoshi Yasunaga
  ``A FPGA-Based Learning Accelerator for Self-Organizing Map and Its Application to Trend-Visualization''
  IEEE 42nd International Conference on Consumer Electrornics (ICCE-2024), 5 pages, Las Vegas, United States, 2024
• Kenji Kanazawa
  ``Solving Maximum Clique Problems using FPGA Based on Swap-Based Tabu Search''
  1st International Workshop on Heuristic Search in Industry (HSI 2020), held in conjunction with IJCAI-2020, 7 pages, Yokohama, Japan, 2021
• Kenji Kanazawa
  ``Accelerating Swap-Based Tabu Search for Solving Maximum Clique Problems on FPGA''
  17th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA 2019), pp.1033-1040, Xiamen, China, 2019
• Kenji Kanazawa and Shaowei Cai
  ``FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT''
  IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), pp.217-224, Hanoi, Vietnam, 2018
• Kenji Kanazawa
  ``Acceleration of Solving Quadratic Assignment Problems on Programmable SoC using High Level Synthesis''
  4th International Workshop on FPGAs for Software Programmers (FSP 2017), pp.40-47, Ghent, Belgium, 2017
• Shohei Sassa, Kenji Kanazawa, Shaowei Cai and Moritoshi Yasunaga
  ``An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search''
  ACM SIGARCH Computer Architecture News 44(4), pp.32-37
  (Post Proceedings of 7th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2016), Hong Kong, 2016)
• Kenji Kanazawa, Kahori Kemmotsu, Yamato Mori, Noriyuki Aibe and Moritoshi Yasunaga
  ``High-Speed Calculation of Convex Hull in 2D Images Using FPGA''
  Parallel Computing with FPGAs, held in conjunction with ParCo2015 (ParaFPGA2015), pp.533-542, Edinburgh, Scotland, United Kingdom, 2015
• Kenji Kanazawa and Tsutomu Maruyama
  ``FPGA Acceleration of SAT/MaxSAT Solving using Variable-way Cache''
  24th International Conference on Field Programmable Logic and Applications (FPL2014), 4 pages, Munich, Germany, 2014
• Katsuyuki Seki, Kenji Kanazawa, and Moritoshi Yasunaga
  "Crosstalk-noise Reduction in GHz Domain Using Segmental Transmission Line"
  2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp.96-99, Nara, Japan, 2013
• Hidefumi Inoue, Moritoshi Yasunaga, Kenji Kanazawa, and Noriyuki Aibe
  "Signal Integrity Evaluation of Segmental Transmission Line under Real-world Application"
  2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp.108-111, Nara, Japan, 2013
• Kazuma Shibasaka, Kenji Kanazawa, and Moritoshi Yasunaga
  "Decoupling-capacitor Allocation Problem Solved by Genetic Algorithm"
  2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS 2013), pp.225-228, Nara, Japan, 2013
• Kenji Kanazawa and Tsutomu Maruyama
  ``Solving SAT-encoded Formal Verification Problems on SoC based on a WSAT algorithm with a new Heuristic for Hardware Acceleration''
  IEEE 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC2013), pp.101-106, Tokyo, Japan, 2013
• Kenji Kanazawa and Tsutomu Maruyama
  ``An FPGA Solver for SAT-encoded Formal Verification Problems''
  21st International Conference on Field Programmable Logic and Applications (FPL2011), pp.38-43, Chania, Crete, Greece, 2011
• Yoshiki Yamaguchi, Kenji Kanazawa, Yoshiharu Ohke and Tsutomu Maruyama
  ``An acceleration method for evolutionary systems based on iterated prisoner's dilemma''
  3rd International Workshop on Applied Reconfigurable Computing (ARC2007), pp.358-364, Rio de Janeiro, Brazil, 2007
  
• Kenji Kanazawa and Tsutomu Maruyama
  ``An FPGA Solver for Very Large SAT Problems''
  17th International Conference on Field Programmable Logic and Applications (FPL2007), pp.493-196, Amsterdam, The Netherlands, 2007
  
• Kenji Kanazawa and Tsutomu Maruyama
  ``An FPGA Solver for Large SAT Problems''
  16th International Conference on Field-Programmable Logic and Applications (FPL2006), pp.303-308, Madrid, Spain, 2006
  
• Kenji Kanazawa and Tsutomu Maruyama
  ``An FPGA Solver for WSAT Algorithms''
  15th International Conference on Field-Programmable Logic and Applications (FPL2005), pp. 83-88, Tampere, Finland, 2005